1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a flash memory device capable of switching wordline and initialization voltages.
2. Description of the Related Art
Flash memory devices are typically used as non-volatile memory devices capable of electrically and repeatedly having data recorded and deleted. Flash memory devices consume less electricity than magnetic disk based storage mediums, and have fast access times like hard disks.
Flash memory devices can be classified as NOR type or NAND type, according to the connection configuration between cells and bit lines. In a NOR type flash memory, two or more cell transistors are connected parallel to one bit line, and data is stored using a channel hot electron method and data is deleted using a Fowler-Nordheim (F-N) tunneling method. In a NAND type flash memory, two or more cell transistors are serially connected to one bit line and data is stored or deleted using an F-N tunneling method. In general, NOR type flash memory devices have relatively large electrical consumption and thus are not suitable for highly integrated devices, but have quick response times. In contrast NAND type flash memories use smaller cell current and are suitable for highly integrated devices.
FIG. 1A is a circuit diagram illustrating a memory cell structure of a general NAND type flash memory. In FIG. 1, multiple wordlines WL11 through WL14 and multiple memory cells M11 through M14 are illustrated. With selection transistors ST1 and ST2, the memory cells M11 through M14 constitute a string, and are serially connected between a bit line BL and a ground voltage VSS.
FIG. 1B is a circuit diagram illustrating a memory cell structure of a NOR type flash memory device. As illustrated in FIG. 1B, in the NOR type flash memory device, memory cells M21 through M25 and M22 through M26 are respectively connected between bit lines BL1 and BL2 and source lines CSL.
The above flash memory devices, particularly the NOR type flash memory device, can be used for the purpose of storing a code. In storing a code, it is important to have high operation speed without delay during a read operation. To this end, a wordline voltage applied to a wordline of a cell is always generated and retained, even in standby, during a read operation. The wordline voltage is provided as a power source voltage of a decoder (row decoder). Accordingly, when a command for a read operation is applied to the flash memory device, the read operation can be immediately operated without any delay to generate a high voltage wordline.
Meanwhile, one method of increasing the storage capacity of a flash memory device incorporates use of a multi-level cell (MLC) method. In the MLC method, one cell is programmed to have various threshold voltages to store two or more multi-bits in one memory cell, which is different from a single level cell (SLC) method, which only stores one bit in one memory cell.
For example, when two-bit data is stored in one MLC, four voltage thresholds are employed. Therefore, in order to read data stored in the cell, wordline voltages having three different levels are required. A stable read operation can be performed when the wordline voltages are maintained at uniform values.
FIG. 2A is a block diagram illustrating a portion of a flash memory device for explaining a conventional method of generating a wordline voltage. FIG. 2B is a waveform diagram for illustrating levels of wordline voltages that may be generated, in accordance with the conventional method.
As illustrated in FIG. 2A, a general memory device includes a wordline voltage generating unit 11, a switch unit 12, and a row decoder 13. The wordline voltage generating unit 11 generates one or more wordline voltages Vread 1 through Vread 3, usually by using a charge pump and a voltage regulator circuit (not shown). In a general voltage regulator circuit, a voltage higher than a target output voltage is used as a power source to provide a charge to an output end when the output voltage is lower than the target voltage to increase the output voltage. When the output voltage has approximately reached the target output voltage, charges are blocked to prevent further voltage increase.
In the above structure, when an output voltage is undesirably increased due to charge flowing to the output end, no measure for reducing the increased output voltage is provided. For example, wordline voltages Vread 1 through Vread 3, which are generated in the wordline voltage generating unit 11 for a read operation, are sequentially provided to the row decoder 13 by a switching operation of the switch unit 12. After the wordline voltage Vread 1 (having a low voltage level) through the wordline voltage Vread 3 (having a high voltage level) are sequentially switched, a parasitic capacitance Ca, which is present at an output node Na of the switch unit 12, obtains a voltage that corresponds to the wordline voltage Vread 3.
When a new read operation is performed, a charge sharing is generated between the parasitic capacitance Ca component of the node Na and a capacitance Cb component of an output node Nb of the wordline voltage Vread 1, thus minutely increasing the level of the wordline voltage Vread 1. That is, as illustrated in FIG. 2B, when the wordline voltage Vread 1 is generated at each cycle of the read operation, the level of the wordline voltage Vread 1 is continuously and minutely increased. Accordingly, the wordline voltage Vread 1 is not stably output.
Since the parasitic capacitance Ca of the output node Na is usually greater than a parasitic capacitance Cb of the node Nb, the aggregate increase in the wordline voltage level over a few read operations may not be significant. However, when the above process is continuously repeated, the wordline voltages, especially the wordline voltage Vread 1, may increase to the point that reliability of the read operations decrease.